Posted in 2017

VUnit BFMs - as Simple as Emailing

This article was originally posted on LinkedIn where you may find some comments on its contents.

VUnit BFMs - as Simple as Emailing

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VUnit Matlab Integration

This article was originally posted on LinkedIn where you may find some comments on its contents.

VUnit Matlab Integration

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VUnit 3.0 - While Waiting for VHDL-2017

This article was originally posted on LinkedIn where you may find some comments on its contents.

VUnit 3.0 - While Waiting for VHDL-2017

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VUnit 3.0 Color Logging

This article was originally posted on LinkedIn where you may find some comments on its contents.

VUnit 3.0 Color Logging

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Sigasi Adds Support for VUnit Testing Framework

This article was originally posted on LinkedIn where you may find some comments on its contents.

Sigasi Support

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Enable Your Simulator to Handle Complex Top-Level Generics

A powerful feature in VUnit is the ability to run testbenches and test cases with different configurations (not to be confused with VHDL configurations). The typical use case is to run tests with different generics but you can also run with different simulator settings and register Python functions to be run before and after the test. The latter can be used to create stimuli and verify test outputs using the power of Python or some other external program like Matlab.

Over time VUnit users tend to get more advanced in the use of generics which inevitably leads to more complex data types. Rather than passing many generics of scalar types they want to create composite types like records and arrays. Unfortunately, many simulators have restrictions on what type of generics you can pass to the top-level testbench entity. Typically you’re limited to a small subset of the standard composite types like string and std_logic_vector and can’t use custom composite types. This is a limitation when trying to write clean and efficient code but something that can be worked around using VUnit. The trick is to encode your composite data type into something that the simulator _can_ handle and then decode back to the original type within the VHDL testbench. string is something most (all?) simulators can handle and what I will use in these examples.

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VUnit - Getting Started 1-2-3

I recently a started a LinkedIn blog series about getting started with VUnit. The first three parts are:

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