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VUnit cosim
===========

**VUnit** is an open source unit testing framework for VHDL/SystemVerilog, which features the
functionality needed to realise continuous and automated testing of HDL code.
VUnit doesn't replace but rather complements traditional testing methodologies by
supporting a *"test early and often"* approach through automation. :ref:`Read more <vunit:about>`

**VUnit cosim** follows the same philosophy to support co-simulation (co-execution) of VHDL along with
software applications written in a different language (typically C/C++ or Python). The content of this module is organised in bridges, examples and utils:

* :ref:`bridges`: glue logic between a :ref:`external VHDL API <vunit:data_types_library>` (or another bridge) and some other API in VHDL and/or C (bindings).

* :ref:`examples`: working demo projects that use some utils and/or bridges.

* :ref:`utils`: helper functions in Python (based on ctypes, base64, numpy and Pillow) which are useful for interacting with C-alike executables.

.. toctree::
   :maxdepth: 3
   :hidden:

   bridges/index
   examples/index
   utils
   genindex
   py-modindex