Release notes¶
For installation instructions read this.
4.0.6 - 2018-11-15 (latest)¶
- Fix a problem where sometimes multiple Ctrl-C where required to abort execution. #408
4.0.2 - 2018-10-25¶
- Fix missing msg_type in push and pop of msg_t.
- Ensure axi_lite_master always aligns with aclk to avoid VHDL/Verilog simulation mismatch.
4.0.1 - 2018-10-23¶
- Set value to null when pushing pointer types in queue_t and com to avoid accidental dupliction of ownership.
- Fix broken ram_master.vhd where the response messages where deleted to early.
4.0.0 - 2018-10-22¶
New coverage support:
The
--coverageflag has been removed in favor of exposing a more flexible coverage interface. The flag was was not flexible enough for many users and we decided to make a breaking change to get a better solution moving forward. An example of using the new interface can be found here here. For users who liked the old flag VUnit supports adding custom command line arguments.Add ability to set watchdog timer dynamically. #400
Skipping protected regions in the Verilog preprocessor.
Integrate utility to add Vivado IP to a VUnit project see example.
Make tb_path work in combination with preprocessing. #402
3.9.0 - 2018-10-11¶
- Verification components
- Avalon
- Add Avalon streaming packet signals #383
- AXI
- Various AXI BFM improvements.
- Added special JUnit XML format for Bamboo CI server. #384
- Add support for requirements trace-ability via user defined test attributes.
- Add
--json--exportflag to export list of all files and tests with associated attributes. - Add test case filtering for user defined attributes.
- For example allows marking tests that should be run per commit or only every night.
- Always use the most up to date version of modelsim.ini.
3.7.0 - 2018-07-21¶
- Fixed lint issues from new pylint version.
- Log output of failed vsim startup to stderr. #354
- Allow case-insensitive lookup of entities. ##346
- Added vhdl_standard attribute at class initialization. ##350
- Adding csv mapping support for files and libraries. #349
- Fix broken vivado example wrt verilog headers. #344
- Allow adding duplicate libraries. #341
- Make adding duplicate file INFO instead of WARNING. #341
3.6.0 - 2018-06-19¶
- Ignore files added twice with identical contents. Closes #341
- Made queues type safe
3.5.0 - 2018-06-04¶
- Added the ability to specify actor for AXI stream masters and slaves
- Added as_sync function to bus masters and AXI stream masters
3.3.0 - 2018-05-24¶
- Add SystemVerilog support for test benches without test cases. #328
- Graceful recovery and error message from failed VHDL parsing.
- Stripping clean from re-compile command.
- Add JSON-for-VHDL as a submodule.
3.1.0 - 2018-04-27¶
- Add
--fail-fastCLI argument to stop on first test failure. - Delay simulator selection until VUnit class instantiation instead of import
- Add
post_runto VUnit main. - Add
disable_coveragecompile option. - Improve AXI read/write slaves
- Add debug logging
- Add setting of stall, fifo depth and response latency
- Add burst length statistics
- Improve AXI-lite master
- Add debug logging
3.0.3 - 2018-04-22¶
- Add
check_equalfor real withmax_diff - Improve
comlibrary performance - Added support for message forwarding
- Improve axi stream verification components
- Add wishbone verification component
- Protect against unexpected mutation of compile and sim options
3.0.2 - 2018-02-22¶
- Added is_empty on queues
- Documented queue_t and integer_array_t
- Fixed memory leak
3.0.0 - 2018-02-12¶
- beta version of a verification component library.
- AXI read/write slaves
- Memory model
- AXI master
- AXI stream
- UART RX/TX
- (B)RAM master
- Hiearchical and color logging support.
- Communication library usability improvements.
- Push/pop message creation and debugging tools.
2.4.3 - 2018-01-24¶
- SystemVerilog: Fix dependency scanning with instance directly after block label #305.
2.4.0 - 2018-01-12¶
- Ignore test cases in SystemVerilog comments.
- Make integer_array_t metadata get-functions public.
- dictionary: add default value option to get function.
- Improve get_implementation_subset #286.
2.3.0 - 2017-12-19¶
- Fix commas in Modelsim generics #284.
- Fix problem with vsim_extra_args between entity and architecture in riviera and activehdl.
- Update Verilog preprocessor to read using latin-1 encoding. #285.
- Improve compile printouts #283.
- Add -q/–quiet flag. #283.
- Add printout of output file location. #283.
- Dropped support and testing of Python 3.3 (might still work anyway).
- Fix of Modelsim –coverage argument #288.
2.2.0 - 2017-09-29¶
- Add support for tokenizing verilog multi line strings. #278
- Added support for restarting window in check_stable
- Added support for num_cks=0 in check_next.
- Error on adding duplicate source files. #274
- Update Vivado example.
- Add support for non-system-verilog verilog files. #268
- Add dependency scanning of the use of an instantiated package. #233
- Add human readable test output paths. #211
2.1.1 - 2017-07-19¶
2.1.0 - 2017-07-19¶
- Add
{rivierapro, modelsim}_init_files.after_loadsim_options. They allow setting a list of DO/TCL files to be executed duringvunit_loadafter the top level has been loaded using thevsimcommand. - Add input validation to sim and compile options
2.0.0 - 2017-02-21¶
Public interface changes¶
Some run.py scripts can be broken by this. Both set_generic
and add_config works differently internally.
set_generic and set_sim_option now only affects files added
before the call so reordering within the run.py can be needed.
add_config on the test case level will no longer discard
configurations added on the test bench level. This affects users
mixing adding configurations on both test and test case level for the
same test bench. Adding a configuration on the test bench level is now
seen as a shorthand for adding the configuration to all test cases
within the test bench. Configurations are only held at the test case
level now. Before there could be configurations on multiple levels
where the most specific level ignored all others. I now recommend
writing a for loop over test_bench.get_tests() adding configurations
to each test individually, see the updated generate_tests example.
We have also forbidden to have configurations without name (“”), this
is since the default configuration of all test cases has no name. The
post_check and pre_config can now be set using
set_pre_config also without using add_config removing the need
to add a single unnamed configuration and instead setting these in the
default configuration.
This internal restructuring has been made to allow a sane data model of configurations where they are attached to test cases. This allows us to expose configurations objects on the public API in the future allowing users more control and visibility. The current behavior of configurations is also better documented than it ever was.
I suggest reading the section on configurations in the docs.
- Replace
disable_ieee_warningsandset_pliwith corresponding simulation options. - Adds
--versionflag - Added
--guiflag for GHDL to open gtkwave. Also allows saving waveform without opening gui with--gtkwave-fmtflag.
1.4.0 - 2017-02-05¶
- Removed bug when compiling Verilog with Active-HDL
- Updated array package
- Added support for simulation init script
- Added support for setting VHDL asserts stop level from run script
1.3.0 - 2017-01-06¶
- Added support for pass acknowledge messages for check subprograms.
- Made design unit duplication a warning instead of runtime error again.
1.1.1 - 2016-12-08¶
- Adds vunit_restart and vunit_compile TCL commands for both ModelSim and RivieraPro
- Also support persistent simulator to save startup overhead for RivieraPro.
- Changes –new-vsim into -u/–unique-sim which also works for riviera
1.0.0 - 2016-11-22¶
- Adds ActiveHDL custom simulation flags support
- Made library simulator flag argument deterministic and same as the order added to VUnit
- Added check_equal between std_logic_vector and natural for unsigned comparison
- Can now set vhdl_standard on an external library
- Added no_parse argument to add_source_files(s) to inhibit any dependency or test scanning
- Renamed public method depends_on to add_dependency_on
0.70.0 - 2016-10-13¶
- Hashing test output_path to protect against special characters and long paths on Windows.
- Added
.voas recognized Verilog file ending. - Enable setting vhdl_standard per file.
0.67.0 - 2016-08-08¶
- A number of minor enhancements and bug fixes
- Added vunit_restart TCL procedure to ModelSim
- Print out remaining number of tests when pressing ctrl-c
- Updated OSVVM and made it a git submodule. Run
git submodule update --init --recursive
after updating an existing Git repository or
git clone --recursive https://github.com/VUnit/vunit.git
when creating a new clone to get the OSVVM subdirectory of VUnit populated. Doesn’t affect installations made from PyPi
0.65.0 - 2016-03-13¶
- Added sim and compile options to set rivierapro/activehdl flags. #143.
- Removed builtin
-dbgflag to vcom for aldec tools. Use set_compile_option instead to set it yourself. - Fixed a bug with custom relative output_path.
- Documentation fixes & improvements.
- Update rivierapro and activehdl toolchain discovery. #148.
- Added possibility to set
VUNIT_<SIMULATOR_NAME>_PATHenvironment variable to specify simulation executable path. #148. - Added
-k/--keep-compilingflag. #140. - Added optional
output_pathargument topre_config. #146.
0.64.0 - 2016-03-03¶
- Added python version check. Closes #141.
- Not adding .all suffix when there are named configurations
0.61.0 - 2016-02-23¶
- Adds
.allsuffix to test benches with no test to better align with XUnit architecture. - Enables better hierarchical JUnit XML report view in Jenkins. - Fixes #129.
0.60.0 - 2016-02-15¶
0.59.0 - 2016-02-13¶
- Covered a miss in circular dependency detection.
- Added detection of circular includes and macro expansions in verilog preprocessing.
- Added caching of verilog parse results for significant speed when running run.py more than once.
0.57.0 - 2016-02-08¶
- Adds
include_dirsargument also toLibraryadd_source_file(s) - Ignores more builtin Verilog preprocessor directives.
0.54.0 - 2016-02-06¶
- Adds support for Verilog preprocessor ifdef/ifndef/elsif/else/endif
- Fixes regression in modelsim persistent mode. Makes many short tests faster.
0.53.0 - 2016-02-06¶
add_source_filesaccepts a list of files- Added
-f/--filescommand line flag to list all files in compile order - Verilog parser improvements in robustness and error messages.
