What is VUnit?

VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn’t replace but rather complements traditional testing methodologies by supporting a “test early and often” approach through automation.

NOTE: SystemVerilog support is experimental.

Project Mission

The VUnit project mission is to apply best SW testing practices to the world of HDLs by providing the tools missing to adapt to such practices. The major missing piece is the unit testing framework, hence the name V(HDL)Unit. However, VUnit also provides supporting functionality not normally considered as a part of a unit testing framework.

Main Features

  • Builds on the commonly used xUnit architecture.
  • Python test runner that enables powerful test administration, can handle fatal run-time errors (e.g. division by zero), and ensures test case independence.
  • Scanners for identifying files, tests, file dependencies, and file changes enable automatic (re)compilation and execution of test suites.
  • Can run test cases in parallel to take advantage of multi-core machines.
  • Scriptable API as well as command line support.
  • Support for running same test suite with different generics.
  • VHDL test runner which enables test execution for not fully supported simulators.
  • Assertion checker library that extends VHDL built-in support (assert).
  • Logging framework supporting display and file output, different log levels, filtering on level and design hierarchy, output formatting and multiple loggers. Spreadsheet tool integration.
  • Location preprocessor that traces log and check calls back to file and line number.
  • JUnit report files for better Jenkins integration.

Requirements

VUnit depends on a number of components as listed below. Full VUnit functionality requires Python and a simulator supported by the VUnit Python test runner. However, VUnit can run with limited functionality entirely within VHDL which means that unsupported simulators can be used as well. Prototype work has been done to fully support other simulators but this work is yet to be completed and released.

Languages

  • VHDL-93
  • VHDL-2002
  • VHDL-2008
  • Verilog
  • SystemVerilog

Operating systems

  • Windows
  • Linux
  • Mac OS X

Python

  • Python 2.7
  • Python 3.3 or higher

Simulators

  • Aldec Riviera-PRO
    • Tested with Riviera-PRO 2015.06, 2015.10, 2016.02, 2016.10 (x64/x86).
    • Only VHDL
  • Aldec Active-HDL
    • Tested with Active-HDL 9.3, 10.1, 10.2, 10.3 (x64/x86)
    • Only VHDL
  • Mentor Graphics ModelSim/Questa
    • Tested with 10.1 - 10.5
  • GHDL
    • Only VHDL
    • Works with versions >= 0.33
    • Tested with LLVM and mcode backends, gcc backend might work aswell.
    • Integrated support for using GTKWave to view waveforms.
  • Cadence Incisive (Experimental)
    • Community contribution. VUnit maintainers does not have access to this simulator to verify the functionality.
    • Run incisive_vhdl_fixup.py to remove VHDL constructs that are not compatible with Incisive

Getting Started

There are a number of ways to get started.

Support

Any bug reports, feature requests or questions about the usage of VUnit can be made by creating a new issue.

Main Contributors

  • Lars Asplund
  • Olof Kraigher

License

VUnit

VUnit except for OSVVM (see below) is released under the terms of Mozilla Public License, v. 2.0.

© 2014-2017 Lars Asplund, lars.anders.asplund@gmail.com.

OSVVM

OSVVM 2015.03 is redistributed with VUnit for your convenience. Minor modifications have been made to enable GHDL support. Derivative work is also located under examples/vhdl/osvvm_integration/src. These files are licensed under the terms of ARTISTIC License.

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