JSON-for-VHDL library which can be used to parse JSON content.
The content can be read from a file, or passed as a stringified generic.
This is an alternative to composite generics, that supports any depth in the content structure.
The most minimal VUnit VHDL project covering the basics of the User Guide.
Demonstrates the VUnit run library.
Demonstrates VUnit’s support for logging.
A more realistic test bench of an UART to show VUnit VHDL usage on a typical module.
integer_array_t data type, which can be used to
handle dynamically sized 1D, 2D and 3D data as well as storing and
loading it from csv and raw files.
Demonstrates generating multiple test runs of the same test bench
with different generic values. Also demonstrates use of
to create test bench output files in location specified by VUnit python runner.
Demonstrates the AXI read and write slave verification components as well as the AXI-lite master verification component. An AXI DMA is verified which uses an AXI master port to read and write data from external memory. The AXI DMA also has a control register interface via AXI-lite.
Shows how to use
A CSV file is read, the content is sent in a row-major order to an AXI Stream buffer
(FIFO) and it is received back to be saved in a different file. Further information can
be found in the verification component library user guide,
in subsection Stream and in
Demonstrates the VUnit check library.
Demonstrates compiling and performing behavioral simulation of Vivado IPs with VUnit.
com message passing package which can be used
to communicate arbitrary objects between processes. Further reading
can be found in the com user guide.
The most minimal VUnit SystemVerilog project covering the basics of the User Guide.
A more realistic test bench of an UART to show VUnit SystemVerilog usage on a typical module.