HDL Libraries#



By default, VUnit provides bare minimal functionality for running testbenches. In practice, most users want to use HDL utilities to reduce verbosity and improve reporting when writting tests. VUnit includes several optional libraries in a group named VHDL builtins (see add_vhdl_builtins()):

Most of the utilities are based on some internal data types providing dynamic arrays and queues (FIFOs). See Data Types User Guide.


The VUnit communication library (com) provides a high-level communication mechanism based on the actor model.

See add_com() and Communication Library User Guide.


The Communication Library depends on the builtins, which are added implicitly.

Verification Components#


This library is released as a BETA version. This means non-backwards compatible changes are still likely based on feedback from our users.

The VUnit Verification Component Library (VCL) contains a number of useful Verification Components (VC) as well as a set of utilities for writing your own verification component. Verification components allow a better overview in the test bench by raising the abstraction level of bus transactions. Even if you do not need the advanced features that VCs offer you may still benefit from using peer-verified models of an AXI-bus instead of re-implementing it yourself.

See add_verification_components() and Verification Components User Guide.


The VCL depends on both the Communication Library and OSVVM, which are added implicitly.


VUnit provides random integer vector and pointer generation, based on built-in Data Types and OSVVM.

See add_random().


VUnit includes the core of OSVVM as a submodule and internal dependency of optional libraries such as Random or Verification Components. However, it can be added explicitly through add_osvvm().

Moreover, multiple approaches are supported for using OSVVMLibraries in VUnit. See OSVB: Examples » SISO AXI4 Stream.


VUnit includes JSON-for-VHDL as a submodule. JSON-for-VHDL is an alternative to composite top-level generics, which supports any depth in the content structure.

See add_json4vhdl(), json4vhdl.py and example JSON-for-VHDL.

System Verilog#


See add_verilog_builtins() and vunit_pkg.sv.