Release notes

Note

For installation instructions read this.

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Features

• [GHDL/NVC] Arbitrary waveform viewers are now supported by passing the --viewer command line argument. As a consequence, ghdl.gtkwave_script.gui and nvc.gtkwave_script.gui are deprecated in favour of ghdl.viewer_script.gui and nvc.viewer_script.gui, respectively. The --gtkwave-args and --gtkwave-fmt command line arguments are deprecated in favour of --viewer-args and --viewer-fmt, respectively. ghdl.viewer.gui and nvc.viewer.gui can be used to set the preferred viewer from the run-file. If no viewer is explicitly requested, gtkwave or surfer is used, in that order. This also means that VUnit now uses surfer if gtkwave is not installed.

  [NVC] It is possible to get VCD waveform files by passing --viewer-fmt=vcd. (#1002)

• Added timeout parameter to the wait_until_idle procedure in the synchronization verification component interface. A timeout will result in a failure. (#1054)

Commits since last release

5.0.0.dev3 - PRE-RELEASE - 2024-08-15 (latest)

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Features

• Added option to configure the logging simulation time format (unit and number of decimals). (#1044)

• Added support for setting run_all_in_same_sim and fail_on_warning attributes from Python. (#1053)

5.0.0.dev2 - PRE-RELEASE - 2024-08-07

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Breaking Changes

• Changed default values for unconnected tkeep and tstrb inputs for AXI stream VCs to match the standard:

  • tkeep changed from all zeros to all ones

  • tstrb changed from all zeros to value of tkeep

  May affect existing code if these values are verified by the testbench despite being unconnected. (#1049)

Bug Fixes

• Changed AXI stream slave to only verify tdata if both of tkeep and tstrb are set. Removed potential race condition an AXI stream master. (#1049)

5.0.0.dev1 - PRE-RELEASE - 2024-07-19

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Breaking Changes

• HDL builtins are not compiled by default. To preserve the functionality, the run script is now required to explicitly use methods add_vhdl_builtins() or add_verilog_builtins(). (#559, #764, #777)

• [VHDL] Remove array_pkg; use integer_array_t instead. (#600)

• Continue after compilation failure if --keep-compiling is True. (#742)

• [GHDL] Remove ghdl.flags; use ghdl.a_flags instead. (#932)

• [VHDL] Remove deprecated check, log and run packages. (#933)

• Remove 1 ms gate lock timeout. (#983)

Bug Fixes

• [VCs] Take tkeep and tstrb into account when checking for invalid tdata in axi_stream_protocol_checker. (#798, #799)

• [Questa] Added workaround for bit-ordering bug in Questa (#889)

• [GHDL] Create missing directories when generating coverage report. (#924)

• [VHDL] Fixed memory leak in check/log functions. (#954, #956, #1001)

• [OSVVM] Compile correct MemoryPkg files for simulators supporting generic packages. (#965)

• Fixed bug for check_relation when using custom checker. (#971)

• [VC] Fixed failing 4kB boundary check in AXI when using unaligned addresses. (#1018)

Deprecations

• Drop Python v3.6.

Documentation

• Rename ‘VHDL Libraries’ to HDL Libraries. Add section Guides. (#764)

Features

• Added support for simulating top-level VHDL configurations. (#179, #951)

• Add common log interface for third-party logging framework integration. (#776, #947, #949)

• [VCs] Drive axi_lite_master, axi_read_slave and axi_write_slave bus with 'X' when valid is low. (#802, #994)

• [VHDL] Add check_equal for ieee.fixed_pkg types. (#909, #989, #998)

• [NVC] New simulation and compile option nvc.global_flags can be used to pass arbitrary flags to nvc. (#946, #948)

• [Parsing] Allow multiply and divide within component instantiations. (#966)

• [GHDL] Support selecting FST format for waveform files. (#967, #1004)

• Add py.typed file to indicate the existence of Python typing hints. (#991)

• [GHDL] Add support for mcode JIT in backend detection. (#1005)

• [GHDL] Added coverage support for mcode backend. (#1007)

• Update time reporting from test results. Also add timestamps when starting tests. (#1025)

• [Active-HDL] Added vunit_help, vunit_load, vunit_run, vunit_compile, vunit_restart, and vunit_user_init TCL commands to Active-HDL. (#1032)

• [Riviera-PRO, ModelSim/Questa, Active-HDL] Defined the TCL variable vunit_tb_name as the name of the top level design unit during the evaluation of the <simulator>.init_file scripts for Active-HDL, Riviera-PRO and ModelSim/Qusta. [Active-HDL] Defined the TCL variable vunit_tb_path during the evaluation of the activehdl.init_file.gui script. (#1033)

• [NVC] VUnit now sets the NVC_CONCURRENT_JOBS environment variable to the value of the --num-threads argument which allows nvc to scale its worker thread count based on the number of concurrently running simulations. (#1036)

• It is possible to use all logical CPUs by passing -p0 (--num-threads=0). See multiprocessing.cpu_count for how the number is determined. (#1039)

Miscellaneous

• [NVC] Multi-word command line arguments are now quoted in the log. (#940)

• Removed unused code. (#972)

• [Questa/Modelsim] Remove compile warnings. (#981, #993, #996)

• [VHDL] Minimize imports in packages and VCs in an effort to reduce simulator startup time. (#992)

• Improved error message when entity name in architecture statement is misspelled such that there is no matching entity. (#1026)

• [OSVVM] Bump to 2023.04.

4.7.0 - 2023-04-23

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Bug Fixes

• [JSON-for-VHDL] Fix invalid XML characters in the example. (#356, #845)

• Fix AXI Stream slave back to back transfers. (#573, #858)

• [Riviera-PRO] Fix for RUNTIME_0232 and RUNTIME_022 messages. (#621, #825)

• Fix delta cycle race conditions. (#642, #813)

• Skip non-generic OSVVM packages when the simulator supports generics. (#768, #769)

• Fix location preprocessor casing bug. (#773, #774)

• Support detecting and failing on ambiguous direct entity instantiations. (#781)

• [Vivado] Add flag fail_on_non_hdl_files. (#782, #786)

• Fix parsing of port type starting with signal. (#792, #826)

• Fix false pass. (#794)

• Fix axi_lite_master wait behaviour if idle. (#797, #856)

• Handle PermissionError while listing available simulators. (#819, #820)

• [ModelSim/Questa] Workaround for compilation bug. (#838, #840)

• Support generics with explicit constant declaration. (#852, #854)

• Detect GHDL backend with newer GCC|LLVM. (#898, #901)

Deprecations

• Add compile_builtins deprecation warning. Use add_vhdl_builtins and/or add_verilog_builtins instead. (#559, #757, #777, #778)

• [OSVVM] Bump to 2022.04. (#754, #780, #790, #827)

• Python 3.6 was EOL in Dec 2021; use Python 3.7 as the minimum tested version.

• [JSON-for-VHDL] Bump to 95e848b8.

Documentation

• Add timing diagrams to the Check Library user guide. (#576, #823)

• Add add_vhdl_builtins and add_verilog_builtins. (#757)

• Add section Overview, including a diagram. (#779)

• Improve documentation for pre_config and post_check. (#801, #849)

• Improve help of CLI option --clean. (#810, #855)

• Added LibraryList. (#816)

• Fix typos. (#821, #832)

• Clarify that VUNIT_SIMULATOR is set to modelsim when using Questa. (#834, #850)

• Improve documentation of check_enabled. (#874)

• Added Identity package user guide. (#887, #888)

• Change theme to furo. (#912)

• Add blog post on FPGA World 2022 in Stockholm.

• Add blog post on VUnit’s relation to other frameworks.

Features

• Add NVC simulator support. (#44, #904, #914, #926, #927, #930)

• Skip addition of built-in dependencies (OSVVM and/or JSON-for-VHDL) if the library is added previously. (#767, #771)

• Add method to get list of libraries from VUnit object. (#815)

• Make dict_t type generic. (#830, #835)

• Add support for byte enable to Avalon slave. (#872)

• [Active-HDL] Enable VHDL-2019. (#875)

• Add high-level event synchronization mechanism. (#883)

• Add Identity package. (#887)

• Add phases for better runtime control. (#900)

• [VHDL-2019] Support interface lists with trailing comma. (#903)

• [VHDL-2019] Add method supports_vhdl_call_paths to the simulator interface. (#908)

• Introduce new class LibraryList and add method to get list of libraries from VUnit object.

Miscellaneous

• Replace inspect.getargspec method, removed in Python 3.11. (#868)

• Test support on Python 3.11. (#870)

• [CI] Add workflow_dispatch. (#911)

• [CI] Add NVC jobs. (#917)

• Improved release notes by adding sections using towncrier to aid in finding relevant information about releases and updated contributing guide with instructions. (#918, #921)

• [CI] Forks push the docs to branch gh-pages (so it’s published at <USERNAME>.github.io/vunit). (#920)

• Add utilities to create HTML from code snippets and VUnit logs.

4.6.0 - 2021-10-25

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• Add Python 3.9 and 3.10 to classifiers.

• Use MAJOR and MINOR constants to check supported Python version. #724

• Fix pylint issues.

• Use f-strings for string formatting. #743 #747

• Specify encoding when using ‘open’. #748

• Set black line-length to 120 characters. #736

• Use Path from pathlib, instead of open().

• Add support for log location based on VHDL-2019 call paths. #729

• GHDL supports VHDL package generics. #753

• Bump OSVVM to 2021.09.

• [Tox] Use pytest for collecting coverage, add py310.

• [Tests] mark array_axis_vcs and verilog_ams examples as xfail. #751

• [Logging/log_deprecated_pkg] fix compilation issues with Cadence tools. #731

• [Parsing/tokenizer] partial revert of 5141f7c #735 #745

• [UI] make glob search recursive by default.

• [VCs] bugfix AXI stream slave nonblocking check. #720

• [Examples] add shebang to run scripts. #738

• [Example/vhdl/user_guide] add VHDL 1993 variant, clean use statements, skip in acceptance tests if VHDL context not supported. #737

• [Examples/vhdl/array_axis_vcs] Fix PSL check for valid fifo in data during write. #750 #766

• [Docs] bump sphinx_btd_theme to v1, revert temporary pinning of Sphinx and docutils, remove redundant delete message call from com user guide example, fix ref to Travis CI (deprecated) (GitHub Actions is used now), add section about envvars, document VUNIT_VHDL_STANDARD, use ‘exec’ directive to generate content in examples, update ‘Credits and License’, add refs to Tratex. #730 #739 #761

• [CI] add emojis/icons, avoid deployments from forks, fix deploy condition event, add job using setup-ghdl-ci, update images from Debian Buster to Debian Bullseye, do not overload image tags.

4.5.0 - 2021-05-21

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• Update year and update license test to 2021.

• Bump OSVVM. #712

• Support Python 3.9.

• Call supports_coverage() rather than returning method object. #638

• Do not use relpath when printing output file. #661

• Make runner.create_output_path a member of TestRunner class and reanme to _get_output_path. #682

• Update check_stable to handle longer time frames. #636

• Add check_equal for character. #721 #722

• Update .gitignore. #641

• Resolve ambiguity between VUnit’s line_vector type and the new standard line_vector type in VHDL-2019. #664

• [Tests] Use str for params to self.check, reduce ‘many_keys’ to avoid failure with latest GHDL.

• [Docs] Travis is not used for releases, use autodoc_default_options instead of (deprecated) autodoc_default_flags, fix duplicated content and index of vunit_cli, add intersphinx mapping to docs.python.org, update ‘Credits’ and ‘License’, use buildthedocs/sphinx.theme, replace LICENSE.txt with LICENSE.rst, replace README.rst with README.md, move ‘Requirements’ from ‘About’ to ‘Installing’, add captioned toctrees, use admonitions, move CI out from CLI and update content, add blog post on continuous integration, clarify that GHDL is a rolling project. #694

• [Tools] raise exception if git not available when creating release notes.

• [Example/vhdl/array_axis_vcs] Update, expand procedure run_test, add stall functionality. #648

• [UI] Fix not serializable path when exporting JSON. #657

• [Tox] add pyproject.toml, use isolated_build, merge tox.ini into pyproject.yml.

• [Setup] Ensure that the source tree is on the sys path.

• [RivieraPro] Fix coverage merge error. #675

• [RivieraPro] handle empty macro. #681

• [RivieraPro] Update VHDL version option in command line interface to work with version 2020.04 and above. #664

• [VCs] Add null AXI stream master and slave constants.

• [VCs] Fix bug in AXI stream protocol checker rule 4.

• [VCs] Add ability to define the actor on new_axi_slave function. #709

• [VCs] Push avalon master read req msg one cycle earlier. #695 #696

• [VCs] Fix broken msg passing in wishbone master. #692 #693

• [CI] Update container registry, use ghcr.io.

• [CI] Pin Sphinx and docutils version to work around theme issues.

4.4.0 - 2020-03-26

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• Update year and update license test to 2020.

• Bump OSVVM to latest version.

• Add possibility to configure random stalls for AXI Stream. #557

• JSON-for-VHDL: use base16 encodings. #595

• First release requiring Python 3.6 or higher. Python 2.7, 3.4 and 3.5 are not supported anymore. #596 #601

• Start adding type annotations to the Python sources; add mypy (a static type checker) to the list of linters. #601 #626

• Move co-simulation (VHPIDIRECT) sources (implementation and example) to VUnit/cosim. #606

• ghdl interface: with ghdl_e, save runtime args to JSON file. #606

• Add missing mode assertions to -93 sources of integer_vector_ptr and string_ptr. #607

• Add method get_simulator_name() to public Python API. #610

• Start replacing join, dirname, etc. with pathlib. #612 #626 #632

• Fix parsing adjacent hyphens in a literal. #616

• Fix ghdl.flags error in documentation. #620

• Rename compile option ghdl.flags to ghdl.a_flags. #624

• Move project.Library to separate file.

• Remove Travis CI and AppVeyor, use GitHub Actions only.

• Remove Sphinx extension ABlog; handle posts as regular pages in subdir blog.

• Update GHDL to v0.37 in Windows CI jobs.

• Fix regression in GHDL (prefix of array attribute must be an object name). #631 #635

• Add code coverage support for GHDL. #627

4.3.0 - 2019-11-30

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• Fix broken vhdl_standard setting in some situations. #594

• Add ‘external modes’ (VHPIDIRECT) to string_ptr and integer_vector_ptr; add byte_vector_prt too. #507 #476

• Add report data to Results object/class. #586

• Use a Python formatter: psf/black. #554

• Refactor vunit/ui, vunit/sim_if, vunit/test and tests. #572 #582

• Deprecate array_pkg. It will be removed in future releases. Use integer_array package instead. #593

• Python 3.4 reached End-of-life in 2019-03-18 and it is no longer tested. Support is expected to break in future releases.

• Add support for Python 3.8.

• Deprecate Python 2.7. This is the last release supporting Python 2 and Python 3. Upcoming releases will be for Python 3 only.

4.2.0 - 2019-10-12

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• Add -m/--minimal flag to only compile what is necessary for selected tests.

• Fix axi_stream VC for 0-length tid/tdest/tuser.

• Fix work reference for non-lower case library names. #556

• Add init_files.before_run hook to RivieraPRO and ModelSim.

• Do not add extra quotes when invoking a gtkwave subprocess. #563

4.1.0 - 2019-09-29

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• Enhancements to Stream VCI and AXI Stream VCs. (#420, #422, #429, #483)

• Add option ‘overwrite’ to set_sim_option. (#471)

• ActiveHDL: add code coverage support. (#461)

• GtkWave: add sim option ‘ghdl.init_file.gui’. (#459)

• GHDL: add boolean option ghdl.elab_e, to execute ‘ghdl -e’ only. (#467)

• GHDL: with VHDL 2008 nonzero return values produce a fail. (#469)

• Add experimental VHDL 2019 support. (#549)

4.0.8 - 2018-12-04

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• Fix vivado submodule missing from release. #415

• Add support for checking AXI response in axi_lite_master

• Fix bug with coverage flag not working with unique-sim in rivierapro

• Support for Avalon-MM burst transfers

• Unsure LICENSE_QUEUE environment variable is in effect for RivieraPRO

4.0.7 - 2018-11-20

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• Fix a problem parsing generics with string containing semi colon. #409

4.0.6 - 2018-11-15

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• Fix a problem where sometimes multiple Ctrl-C where required to abort execution. #408

4.0.5 - 2018-11-07

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• Make tb_path absolute again. #406

• Fix --export-json test location offets for DOS line endings. #437

4.0.4 - 2018-11-05

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• Fix broken ActiveHDL support.

4.0.3 - 2018-11-02

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• Fix set_timeout for large values in ModelSim. #405

4.0.2 - 2018-10-25

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• Fix missing msg_type in push and pop of msg_t.

• Ensure axi_lite_master always aligns with aclk to avoid VHDL/Verilog simulation mismatch.

4.0.1 - 2018-10-23

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• Set value to null when pushing pointer types in queue_t and com to avoid accidental dupliction of ownership.

• Fix broken ram_master.vhd where the response messages where deleted to early.

4.0.0 - 2018-10-22

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• New coverage support:

  The --coverage flag has been removed in favor of exposing a more flexible coverage interface. The flag was was not flexible enough for many users and we decided to make a breaking change to get a better solution moving forward. An example of using the new interface can be found here here. For users who liked the old flag VUnit supports adding custom command line arguments.

• Add ability to set watchdog timer dynamically. #400

• Skipping protected regions in the Verilog preprocessor.

• Integrate utility to add Vivado IP to a VUnit project see example.

• Make tb_path work in combination with preprocessing. #402

3.9.0 - 2018-10-11

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• Verification components

  • Avalon

    • Add Avalon streaming packet signals #383

  • AXI

    • Various AXI BFM improvements.

• Added special JUnit XML format for Bamboo CI server. #384

• Add support for requirements trace-ability via user defined test attributes.

• Add --json--export flag to export list of all files and tests with associated attributes.

• Add test case filtering for user defined attributes.

  • For example allows marking tests that should be run per commit or only every night.

• Always use the most up to date version of modelsim.ini.

3.8.0 - 2018-08-26

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• Verification components

  • Avalon

    • Add Avalon memory mapped slave and master. #359

    • Add Avalon stream source and sink. #361

  • AXI

    • Add AXI stream monitor

  • Wishbone

    • Strict command order in wishbone master. #372

• Remove warnings when using built-in RivieraPRO libraries. #374

3.7.0 - 2018-07-21

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• Fixed lint issues from new pylint version.

• Log output of failed vsim startup to stderr. #354

• Allow case-insensitive lookup of entities. ##346

• Added vhdl_standard attribute at class initialization. ##350

• Adding csv mapping support for files and libraries. #349

• Fix broken vivado example wrt verilog headers. #344

• Allow adding duplicate libraries. #341

• Make adding duplicate file INFO instead of WARNING. #341

3.6.2 - 2018-06-21

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• Fixed memory leak when popping messages from queues.

3.6.1 - 2018-06-20

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• Increase message id on publish

3.6.0 - 2018-06-19

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• Ignore files added twice with identical contents. Closes #341

• Made queues type safe

3.5.0 - 2018-06-04

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• Added the ability to specify actor for AXI stream masters and slaves

• Added as_sync function to bus masters and AXI stream masters

3.4.0 - 2018-05-31

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• Updated context files

3.3.0 - 2018-05-24

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• Add SystemVerilog support for test benches without test cases. #328

• Graceful recovery and error message from failed VHDL parsing.

• Stripping clean from re-compile command.

• Add JSON-for-VHDL as a submodule.

3.2.0 - 2018-05-07

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• Add output argument to post_check. #332

3.1.0 - 2018-04-27

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• Add --fail-fast CLI argument to stop on first test failure.

• Delay simulator selection until VUnit class instantiation instead of import

• Add post_run to VUnit main.

• Add disable_coverage compile option.

• Improve AXI read/write slaves

  • Add debug logging

  • Add setting of stall, fifo depth and response latency

  • Add burst length statistics

• Improve AXI-lite master

  • Add debug logging

3.0.3 - 2018-04-22

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• Add check_equal for real with max_diff

• Improve com library performance

• Added support for message forwarding

• Improve axi stream verification components

• Add wishbone verification component

• Protect against unexpected mutation of compile and sim options

3.0.2 - 2018-02-22

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• Added is_empty on queues

• Documented queue_t and integer_array_t

• Fixed memory leak

3.0.1 - 2018-02-19

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• Replace deprecated aliases with constants to work around Sigasi-limitation.

3.0.0 - 2018-02-12

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• beta version of a verification component library.

  • AXI read/write slaves

  • Memory model

  • AXI master

  • AXI stream

  • UART RX/TX

  • (B)RAM master

• Hiearchical and color logging support.

• Communication library usability improvements.

  • Push/pop message creation and debugging tools.

2.4.3 - 2018-01-24

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• SystemVerilog: Fix dependency scanning with instance directly after block label #305.

2.4.2 - 2018-01-20

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• SystemVerilog: Allow MACRO argument within ({[]}). #300.

2.4.1 - 2018-01-16

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• SystemVerilog: Fix WATCHDOG macro with local timescale set #299.

2.4.0 - 2018-01-12

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• Ignore test cases in SystemVerilog comments.

• Make integer_array_t metadata get-functions public.

• dictionary: add default value option to get function.

• Improve get_implementation_subset #286.

2.3.0 - 2017-12-19

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• Fix commas in Modelsim generics #284.

• Fix problem with vsim_extra_args between entity and architecture in riviera and activehdl.

• Update Verilog preprocessor to read using latin-1 encoding. #285.

• Improve compile printouts #283.

• Add -q/–quiet flag. #283.

• Add printout of output file location. #283.

• Dropped support and testing of Python 3.3 (might still work anyway).

• Fix of Modelsim –coverage argument #288.

2.2.0 - 2017-09-29

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• Add support for tokenizing verilog multi line strings. #278

• Added support for restarting window in check_stable

• Added support for num_cks=0 in check_next.

• Error on adding duplicate source files. #274

• Update Vivado example.

• Add support for non-system-verilog verilog files. #268

• Add dependency scanning of the use of an instantiated package. #233

• Add human readable test output paths. #211

2.1.1 - 2017-07-19

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• Fix init_file(s) broken in 2.1.0

• Fix test bench regex that could match *_tb*. #263

• Add external library sanity check. #230

• Add non-empty operation check. #250

2.1.0 - 2017-07-19

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• Add {rivierapro, modelsim}_init_files.after_load sim_options. They allow setting a list of DO/TCL files to be executed during vunit_load after the top level has been loaded using the vsim command.

• Add input validation to sim and compile options

2.0.1 - 2017-07-10

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• Various small fixes

2.0.0 - 2017-02-21

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Public interface changes

Some run.py scripts can be broken by this. Both set_generic and add_config works differently internally.

set_generic and set_sim_option now only affects files added before the call so reordering within the run.py can be needed.

add_config on the test case level will no longer discard configurations added on the test bench level. This affects users mixing adding configurations on both test and test case level for the same test bench. Adding a configuration on the test bench level is now seen as a shorthand for adding the configuration to all test cases within the test bench. Configurations are only held at the test case level now. Before there could be configurations on multiple levels where the most specific level ignored all others. I now recommend writing a for loop over test_bench.get_tests() adding configurations to each test individually, see the updated generate_tests example.

We have also forbidden to have configurations without name (“”), this is since the default configuration of all test cases has no name. The post_check and pre_config can now be set using set_pre_config also without using add_config removing the need to add a single unnamed configuration and instead setting these in the default configuration.

This internal restructuring has been made to allow a sane data model of configurations where they are attached to test cases. This allows us to expose configurations objects on the public API in the future allowing users more control and visibility. The current behavior of configurations is also better documented than it ever was.

I suggest reading the section on configurations in the docs.

• Replace disable_ieee_warnings and set_pli with corresponding simulation options.

• Adds --version flag

• Added --gui flag for GHDL to open gtkwave. Also allows saving waveform without opening gui with --gtkwave-fmt flag.

1.4.0 - 2017-02-05

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• Removed bug when compiling Verilog with Active-HDL

• Updated array package

• Added support for simulation init script

• Added support for setting VHDL asserts stop level from run script

1.3.1 - 2017-01-17

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• Fixed compile errors with GHDL 0.33

1.3.0 - 2017-01-06

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• Added support for pass acknowledge messages for check subprograms.

• Made design unit duplication a warning instead of runtime error again.

1.2.0 - 2016-12-19

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• Updated OSVVM submodule

1.1.1 - 2016-12-08

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• Adds vunit_restart and vunit_compile TCL commands for both ModelSim and RivieraPro

• Also support persistent simulator to save startup overhead for RivieraPro.

• Changes –new-vsim into -u/–unique-sim which also works for riviera

1.0.0 - 2016-11-22

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• Adds ActiveHDL custom simulation flags support

• Made library simulator flag argument deterministic and same as the order added to VUnit

• Added check_equal between std_logic_vector and natural for unsigned comparison

• Can now set vhdl_standard on an external library

• Added no_parse argument to add_source_files(s) to inhibit any dependency or test scanning

• Renamed public method depends_on to add_dependency_on

0.71.0 - 2016-10-20

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• Improved location preprocessing control

0.70.0 - 2016-10-13

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• Hashing test output_path to protect against special characters and long paths on Windows.

• Added .vo as recognized Verilog file ending.

• Enable setting vhdl_standard per file.

0.69.0 - 2016-09-09

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Added check_equal for strings.

0.68.1 - 2016-09-03

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New version to fix broken PyPi upload

0.68.0 - 2016-09-03

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Added check_equal for time and updated documentation.

0.67.0 - 2016-08-08

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• A number of minor enhancements and bug fixes

• Added vunit_restart TCL procedure to ModelSim

• Print out remaining number of tests when pressing ctrl-c

• Updated OSVVM and made it a git submodule. Run

git submodule update --init --recursive

after updating an existing Git repository or

git clone --recursive https://github.com/VUnit/vunit.git

when creating a new clone to get the OSVVM subdirectory of VUnit populated. Doesn’t affect installations made from PyPi

0.66.0 - 2016-04-03

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• Fixed #109, #141, #153, #155.

• Fixed relative path for multiple drives on windows.

0.65.0 - 2016-03-13

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• Added sim and compile options to set rivierapro/activehdl flags. #143.

• Removed builtin -dbg flag to vcom for aldec tools. Use set_compile_option instead to set it yourself.

• Fixed a bug with custom relative output_path.

• Documentation fixes & improvements.

• Update rivierapro and activehdl toolchain discovery. #148.

• Added possibility to set VUNIT_<SIMULATOR_NAME>_PATH environment variable to specify simulation executable path. #148.

• Added -k/--keep-compiling flag. #140.

• Added optional output_path argument to pre_config. #146.

0.64.0 - 2016-03-03

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• Added python version check. Closes #141.

• Not adding .all suffix when there are named configurations

0.63.0 - 2016-03-02

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• Update test scanner pattern to be based on runner_cfg. #138

0.62.1 - 2016-02-28

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0.62.0 - 2016-02-27

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• Early runtime error when gtkwave is missing. Closes #137

• Added add_compile_option. Closes #118

0.61.0 - 2016-02-23

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• Adds .all suffix to test benches with no test to better align with XUnit architecture. - Enables better hierarchical JUnit XML report view in Jenkins.

• Fixes #129.

0.60.1 - 2016-02-16

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• Avoids crash with errors in Verilog defines from Python string in run.py

0.60.0 - 2016-02-15

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• Better error messages when there are circular dependencies.

• Added defines argument to add_source_file(s) #126

• Made --files deterministic with Python 3 #116

0.59.0 - 2016-02-13

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• Covered a miss in circular dependency detection.

• Added detection of circular includes and macro expansions in verilog preprocessing.

• Added caching of verilog parse results for significant speed when running run.py more than once.

0.58.0 - 2016-02-11

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• Parsing Verilog package references. #119

• Added scan_tests_from_file public method. #121.

0.57.0 - 2016-02-08

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• Adds include_dirs argument also to Library add_source_file(s)

• Ignores more builtin Verilog preprocessor directives.

0.56.0 - 2016-02-07

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• Verilog preprocessing of resetall / undefineall / undef

0.54.0 - 2016-02-06

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• Adds support for Verilog preprocessor ifdef/ifndef/elsif/else/endif

• Fixes regression in modelsim persistent mode. Makes many short tests faster.

0.53.0 - 2016-02-06

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• add_source_files accepts a list of files

• Added -f/--files command line flag to list all files in compile order

• Verilog parser improvements in robustness and error messages.

0.52.0 - 2016-01-29

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Added function to get the number of messages missed by a com package actor.